synthesis tools造句
例句與造句
- High level synthesis tool can choose best scheme in a large design space
高級綜合工具可以在很大的設計空間中選擇最優(yōu)的設計方案。 - Automatic synthesis tool after validation can eliminate error because of manual work
采用經過驗證的自動綜合工具，可以消除大部分可能由人工帶來的設計錯誤。 - The program deriving dynamic equations runs in puj 800 , double cpu , 256 mb memory . the synthesis tool and cmos chip of xilinx company are applied to design the hardware
本文中的動力學方程推導程序是在p 800 ，雙cpu ， 256兆內存的機器上運行的。硬件的設計是采用xilinx公司的綜合工具與芯片實現的。 - Lastly , we use the high level synthesis tool synplify to test the validity of the improving mcu . according to the synthesis result , the system clock reached about 66mhz
最后,采用synplicity公司的高層綜合工具synplify對所設計的mcu進行了綜合,綜合結果驗證了改進型mcu滿足了要求,工作頻率達到66mhz 。 - We implement des algorithm and 1024 - bit rsa algorithm with verilog hdl , and simulate their fpga implementation with modisim synthesis tool . finally we test the correctness and performance of the implementation method
采用veriloghdl語言編程實現了des算法和1024位rsa算法,并在modelsim綜合仿真工具中對算法的fpga實現方法進行了仿真,檢驗了算法實現方法正確性和性能。 - It's difficult to find synthesis tools in a sentence. 用synthesis tools造句挺難的
- The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool , which has proved the feasibility and correctness of the circuit
采用硬件描述語言vetilog編寫了硬件電路程序，并使用synplicity的綜合工具synplifypro和altera開發(fā)工具quartus對電路系統(tǒng)進行了綜合與仿真驗證，證明了硬件電路的可行性與正確性。 - I described the principles - . characteristics > function ^ system structure and design flow of synthesis in detail o although synthesis tool does an excellent job of converting hdl to gates . the structure of the hdl may not allow tool to meet the designer - specified constraints and very likely to result in an increase in compile time . the startpoint for synthesis affects the quality of results after synthesis , thus , to attain good startpoint the paper presented a lot of coding styles
本文回顧了集成電路設計方法學的發(fā)展，提出了它們的共同點是基于綜合的設計思想，詳細地介紹了綜合的基本原理、特點、作用、綜合的系統(tǒng)結構及設計流程；同時，雖然各公司提供的綜合工具能很好地進行從hdl級的描述到門級的轉換，但是hdl的結構有時會導致綜合的結果難以滿足預先的要求和綜合時間的增加，所以hdl的編碼風格對綜合結果的影響很大。 - Gae is basically a browser - server argumentation system , which supports loosely coupled group ' s activities , including group thinking and group decision modules , called knowledge creation tool and knowledge synthesis tool respectively . knowledge creation tool supports experts divergent thinking and qualitatively analyzing complex problems
基于web的b / s結構的松散耦合的gae系統(tǒng)給用戶提供一個集約化知識支持平臺，系統(tǒng)包括支持群思考和群決策的兩個模塊，分別是知識創(chuàng)造的發(fā)散工具和知識綜合的收斂工具。 - The characteristic of this ba is applying the dual scaling method to visualize the experts " argumentation contents , which can encourage participation , facilitate users assimilate others ideas , and stimulate emergence of more creative ideas . knowledge synthesis tool applies the ahp and ngt method , which are convergent method , to quantitatively testify the structure problems . in a word , gae system is an environment for solving complex problems
發(fā)散工具是專家發(fā)散思考，定性分析復雜問題的“場” ，特點是應用雙尺度法( dualscalingmethod )將專家研討內容加以可視化分析，這種二維圖的表現形式刺激了專家進一步思考，拓寬其思維，幫助他們多視點、多角度、多側面去了解所要解決問題的目標。 - This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
該mvbc系統(tǒng)設計采用業(yè)界通用的自上而下的eda設計方法,電路邏輯實現采用veriloghdl硬件語言描述,功能和時序驗證的動態(tài)仿真采用synopsys公司的vcs ,而邏輯綜合與fpga實現采用altera公司的集成開發(fā)環(huán)境quartusii軟件以及stratixiiep2s15的fpga器件。 - In this project , the kernel chip is xc2vp4 , which is a platform fpga manufac - tured by xilinx co . ise7 . 1i foundation which is the latest and integrated eda devel - oping tool is used in the software developing . modelsim se6 . 0 and ise simulator are the simulation tools . synplify pro8 . 1 and xst are the synthesis tools
本課題硬件采用xilinx公司xc2vp4平臺級fpga為核心控制芯片,軟件采用xilinx公司最新集成化eda開發(fā)工具ise7 . 1ifoundation ,仿真工具modelsimse6 . 0 ,綜合工具synplifypro8 . 1等設計完成,高速電路采用lvds信號進行連接。 - In this thesis , we study viterbi decoding algorithm first , and analyze the structure of viterbi decoder , then based on them , present the front - end asic design of viterbi decoder . during the course of design , design - compiler of synopsys is applied as synthesis tool of the design , verilog - xl of cadence is applied as the simulation tool
本論文首先對viterbi譯碼算法進行深入的研究，分析譯碼器的結構功能，然后對viterbi譯碼器進行asic前端設計，本次設計是以synopsys公司的design - compiler作為綜合工具、以cadence公司的verilog - xl作為仿真驗證工具進行的。